A ferroelectric random access memory uses a ferroelectric capacitor as the storage element of each memory cell. Each memory cell stores a logic state based on the electrical polarization state of the ferroelectric capacitor. The ferroelectric capacitor has a dielectric between its electrodes that comprises a ferroelectric material such as lead zirconate titanate (PZT). When a voltage is applied to the plates of the ferroelectric capacitor, the ferroelectric material is polarized in the direction of the electric field. The switching threshold for changing the polarization state of the ferroelectric capacitor is defined as the coercive voltage. The ferroelectric capacitor exhibits hysteresis and the flow of current to the capacitor depends on its polarization state. If the voltage applied to the capacitor is greater than its coercive voltage, then the ferroelectric capacitor may change polarization states depending on the polarity of the applied voltage. The polarization state is retained after power is removed, thereby providing nonvolatility. The ferroelectric capacitor can be switched between polarization states vary rapidly in about one nanosecond, which is faster than the programming time of most other nonvolatile memories such as Erasable Programmable Read Only Memories, (EPROMs), Electrically Erasable Programmable Read Only Memories (EEPROMs), or flash EEPROMs.
Data stored in a memory cell having a ferroelectric capacitor is read out as follows. First, a voltage is applied across both electrodes of the ferroelectric capacitor. The difference in charges induced on the bit line coupled to the memory cell is sensed. In order to do so, a circuit is needed that generates a reference voltage having a middle value between a voltage corresponding to data `1` and a voltage corresponding to data `0`. Generally, the reference voltage is produced by use of a reference cell that includes a ferroelectric capacitor having the same properties as the ferroelectric capacitor of the memory cell.
A major problem in sensing the polarization state of the ferroelectric capacitor in the memory cell is that the electric field/polarization characteristic loop (hysteresis curve) of the ferroelectric capacitor changes over time due to aging from use or due to aging from being left in a polarization sense for an extended time. Generally, the change in polarization properties with time, results in a collapsing of the hysteresis curve. This is a basic material phenomenon which is due to a non-reversibility in at least a portion of the volume of the ferroelectric material under electric field/polarization cycling. This changing of the ferroelectric material makes it very difficult to use a reference cell to determine the polarization state of the ferroelectric memory cell.
U.S. Pat. No. 5,432,731, entitled FERROELECTRIC MEMORY CELL AND METHOD OF SENSING AND WRITING THE POLARIZATION STATE THEREOF, describes one approach for overcoming the above-described problem. The simplified one capacitor ferroelectric memory cell with reference cell disclosed in the '731 patent is illustrated in FIG. 1. The '731 patent discloses a reference cell 12 having a first switching transistor 35, a second switching transistor 37, and a reference capacitor 39. The gate of the first switching transistor 35 is connected to a REF WORD line 40 and the source is connected to a BITC line 25. One plate of the reference capacitor 39 is connected to ground and the other plate is connected to the drain of the first switching transistor 35 and to the source of the second switching transistor 37. The drain of the switching transistor 37 is connected to a reference potential REF INIT and the gate is connected to receive a reference initialize signal.
The reference cell 12 of the '731 patent is configured such that the bit line BITC is supplied with the reference voltage in accordance with a voltage dumping structure. Such a voltage dumping structure has the following disadvantage. When no power noise is generated during a read operation, the margin between voltages V.sub.BIT and V.sub.BITC on the bit lines BIT and BITC, that is, the sensing margin, may remain constant as shown in FIG. 2. On the other hand, when power noise is generated during the read operation, the voltages V.sub.BIT and V.sub.BITC on the bit lines BIT and BITC change due to the power noise. However, as illustrated in FIG. 2, the bit line BIT may be affected by the power noise faster than the bit line BITC. This is because the voltage on the bit line BIT changes due to a capacitor coupling structure and the voltage on the bit line BITC changes due to a voltage dumping structure. After the reference potential REF INIT is charged on the reference capacitor 39, the voltage thus charged is dumped on the bit line BITC in accordance with the voltage dumping structure. The charge dumping makes the voltage change on the bit lines BIT and BITC due to the power noise appear differently in time from each other. When the power noise arises during the read operation, as illustrated in FIG. 2, the sensing margin between the bit lines BIT and BITC is reduced. A reduction in sensing margin causes read operation failures.